In the recently years, printed circuit boards have been developed toward high-density circuitry and high performance with miniature laminated substrates to be chip carriers for semiconductor packages. In the conventional semiconductor packaging processes, die-attaching materials are pre-formed on a substrate then pre-cured in order to adhere a chip to the substrate. Therefore, substrates will experience various heat treatments during semiconductor packaging processes such as pre-curing and post-curing of die-attaching material, reflow of bumps, curing of encapsulants, etc. However, due to mismatch of CTE (coefficient of thermal expansion) between substrates and other packaging materials such as die-attaching materials, chips and encapsulants, substrates will warpage and deform leading to difficult packaging processes.
As shown in FIG. 1, a substrate 100 for a conventional semiconductor package is formed by lamination, primarily comprising a core layer 110, a first metal layer 120, a second metal layer 130, a first solder mask 140, and a second solder mask 150. The core layer 110 includes glass fibers mixed with epoxy resin located at the intermediate layer of the substrate. Symmetrically, the first metal layer 120 is laminated on the bottom surface of the core layer 110 and the second metal layer 130 is laminated on the top surface of the core layer 110. The metal layers 120 and 130 are copper wiring layers including a plurality of conductive traces. To be more symmetric, the first solder mask 140 and the second solder mask 150 are respectively disposed on the bottom surface and top surface of the substrate 100 where the solder masks 140 and 150 are made of the same isolating material with the same CTE (coefficient of thermal expansion) and thickness to cover the conductive traces of the metal layers 120 and 130 with only a plurality of external pads 121 and a plurality of internal fingers 131 exposed for electrical connections for bonding solder balls 15 and bonding wires 13. Since the substrate 100 is a laminated substrate with symmetric structures, therefore, the impact of substrate warpage on substrate fabricating processes is not obvious.
As shown in FIG. 1 again, in semiconductor packaging processes, an electronic device such as a semiconductor chip 11 is disposed on the substrate 100 by a die-attaching layer 12 where the semiconductor chip 11 has a plurality of bonding pads 11A on its active surface electrically connected to the internal fingers 131 of the substrate 110 by a plurality of electrical connecting components 13 such as bonding wires formed by wire bonding so that the chip 11 is electrically connected with the substrate 100. Then, an encapsulant 14 is formed on the substrate 100 by molding to encapsulate the chip 11 and the electrical connecting components 13 to provide proper protections. Finally, a plurality of external terminals 15 such as solder balls are bonded to the external pads 121 on the bottom of the substrate 100 to form a BGA package.
Accordingly, above-mentioned semiconductor packaging processes include pre-curing and post-curing of the die-attaching layer 12, curing of the encapsulants 14, reflowing of external terminals 15, or TCT (Thermal Cycle Test), the substrate 100 will experience several heat treatments. Since the CTE of the substrate 100 may be different from the one of the die-attaching layer 12 or from the other packaging materials, unbalanced thermal stresses will be generated leading to substrate warpage during packaging processes, especially, when the die-attaching layer 12 is preformed on the substrate 100 and then pre-cured, the volume shrinkage of the die-attaching layer 12 will cause unbalanced stresses on the substrate 100 leading to substrate warpage. Therefore, the packaging yield will be lower due to void generated between the die-attaching layer 12 and the chip 11 during packaging processes.